As per dwc3 databook, delay is required before taking the core out of reset.
This delay is required so that the PHY are stable, and then we can take core
out of reset.
Reference is taken from linux dwc3 code, file: drivers/usb/dwc3/core.c.
Signed-off-by: Sriram Dash <[email protected]>
Signed-off-by: Rajesh Bhagat <[email protected]>
/* reset USB3 phy - if required */
dwc3_phy_reset(dwc3_reg);
+ mdelay(100);
+
/* After PHYs are stable we can take Core out of reset state */
clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
}